The present invention relates to a semiconductor memory device and a manufacturing method thereof, in detail relates to a semiconductor memory device which can be miniaturized and its manufacturing method in which such a semiconductor memory device can be manufactured readily and precisely.
A semiconductor memory device used in great volume for a personal computer, a workstation, a main frame computer and others is a dynamic random access memory (hereinafter called DRAM) consisting of one transistor which functions as a switch and one capacitor as the smallest unit. This DRAM has been heretofore enhanced in the ratio of four times in three years in the degree of integration and at present, the mass production of a 64-megabit DRAM which is to be manufactured using micro-fabrication technology in the next generation and the minimum feature size of which is 0.35 xcexcm is being developed.
Heretofore, the high integration of a semiconductor memory device has been achieved by reducing the device size, however, the amount of charge which can be stored in a capacitor as information is reduced because the area of the capacitor is reduced for miniaturization. As a result, as signal to noise ratio is deteriorated and reliability is deteriorated because a problem such as the signal reversal caused by the incidence of alpha rays occurs, it is indispensable and the greatest task of a semiconductor memory device to secure the sufficient stored charge so as to keep reliability.
The amount of charge stored in a capacitor is determined by the product of the capacity of the capacitor and applied voltage, the capacity of the capacitor is proportional to the area of the capacitor and the dielectric constant of the dielectric film of the capacitor and is inversely proportional to the thickness of the capacitor dielectric film. Therefore, a stacked-type capacitor wherein a part of a capacitor is formed on the switching transistor and an oxide film for device isolation and a trench-type capacitor wherein a deep trench is formed on a semiconductor substrate and the side wall of the trench is utilized as a capacitor are used in a memory device (hereinafter called a memory cell) of a 4- or more-megabit DRAM so as to prevent storage capacity from being reduced by the reduction of the area of a capacitor caused by micro miniaturization. A 64-megabit DRAM can be realized by using a capacitor with such structure.
However, when the area of a memory cell is reduced in the ratio of 1/3of the previous generation according to a trend, even a memory cell using a stereoscopic capacitor such as the stacked-type capacitor and trench-type capacitor cannot compensate the reduction of the area of the capacitor completely and it is difficult to secure required capacity.
To solve such a problem, a charge storage capacitor called a crown type is proposed. This crown-type capacitor is a stereoscopic one utilizing the inner and outer walls of a concave (crown-type) electrode 19 shown in FIG. 2 as the electrode of the capacitor. Referring to FIG. 2, a reference number 1 denotes a semiconductor substrate, 2 denotes an oxide film for device isolation, 3 denotes the gate oxide film of a transistor, 4 denotes the gate electrode of the switching transistor, 5 and 5xe2x80x2 denote a diffused region different from the substrate in a conductivity type, 6 denotes an interlayer dielectric film, 7 denotes a bit line connected to the diffused region 5xe2x80x2, 8 denotes an interlayer dielectric film, 13 denotes metal for connecting the diffused region 5 and the lower electrode of a capacitor, 19 denotes the lower electrode of the capacitor, 20 denotes a capacitor dielectric film, 21 denotes a plate electrode of the capacitor, 22 denotes an interlayer dielectric film, 23 denotes wiring connected to the diffused region of the substrate, 24 denotes an interlayer dielectric film and 25 denotes the uppermost wiring.
Storage capacity can be increased by adopting structure using such a crown-type capacitor electrode 19 for the capacitor of a DRAM, however, not only an extremely complicated process is required to realize such structure, but there exists a problem that there is great step height.
That is, as shown in FIG. 2, great step height is caused by the crown-type electrode 19 between a memory cell (a left section in FIG. 2) and a transistor (a right section in FIG. 2) in the vicinity and as a result, it is difficult to form wiring 23 on this step height. As the depth of the focus of a used reduction projection aligner is shallow and the tolerance of the focus (depth of focus) is small in optical lithography used for forming wiring 23 with a predetermined pattern, this is because it is difficult to focus on both the upper and lower portions of the step height suitably. In addition, this is because the smaller the dimension of a pattern is, the smaller depth of focus is and a range in which a focus is suitably adjusted is further smaller.
To solve such a problem in forming a wiring pattern caused by step height, a method of planarizing the surface of a substrate by a chemical mechanical polishing (CMP) method is proposed and is already applied to planarizing the interlayer dielectric film of the multilayer interconnection of a logic large scale integrated circuit (LSI).
However, it is difficult to apply this CMP method to a substrate wherein the crown-type electrode 19 approximately 1 xcexcm in height is already formed for a variety of reasons. First of all, when mechanical polishing by applying mechanical force is applied to a capacitor wherein a very thin capacitor dielectric film is formed, possibility that a pinhole or a crack is made on the capacitor dielectric film and as a result, failure of electric isolation occurrence is high. Secondly, the internal stress of a thick oxide film is caused because an oxide film with at least a double thickness of step height is required so as to bury a capacitor with large step height in the oxide film and thus failure of electric insulation of the capacitor dielectric film is caused by this large internal stress as described.
A method of lowering the surface of a silicon substrate in a memory cell array in an initial process is proposed in Japanese published unexamined patent application No. Sho 63-266866. However, if step height is large, the method is difficult to apply.
A memory cell provided with the crown-type capacitor is described in Japanese published unexamined patent applications No. Sho62-48062 and No. Sho62-1281268. FIG. 73 shows the plane arrangement of this memory cell and FIG. 74 shows the section viewed along a line X-Xxe2x80x2 in FIG. 73 and the section of the main part of peripheral circuits. The structure of the section shown in FIG. 75 is a prior embodiment utilizing the internal face of a storage electrode in a trench as a capacitor. This structure has an advantage that it is easier in manufacturing than a crown-type capacitor.
Referring to FIGS. 73, 74 and 75, a reference number 101 denotes a silicon substrate, 102 denotes a field oxide film, 103, 104 and 105 denote highly concentrated impurity regions which are a source or a drain, 106 and 107 denote gate electrodes, 111 denotes a storage electrode, 112 denotes the dielectric film of a capacitor, 113 denotes a plate electrode, 114 denotes a silicon oxide film, 127 denotes an active area, 128 denotes a word line, 130 denotes a data line, 129 denotes a contact hole and 131 denotes a connecting hole. As shown in FIGS. 74 and 75, these conventional semiconductor memories wherein a capacitor is formed on a silicon substrate have large step height between a memory cell and its peripheral circuits.
In a trench capacitor cell wherein a capacitor is formed inside a substrate, large step height is not formed on the substrate. Since the storage capacity can be increased by deepening a trench formed on a substrate, the capacity of the storage capacitor can be prevented from being reduced by reducing the area of a cell.
However, as the size of an area in which a trench can be formed is limited, an aspect ratio of which is approximately 40 and a trench which is extremely deep and narrow in width is required to be formed. Further, there are many problems in a process such as an electrode of a capacitor buried in a substrate and the diffused region of a switching transistor are required to be connected in the substrate and practical use is difficult.
If material with a large dielectric constant, for example, lead zirconate titanate (PZT) which is a ferroelectric substance and others are used for a capacitor dielectric film, large storage capacity can be realized without the complicated shape of a capacitor.
However, a film consisting of noble metal such as platinum is required to be used for the electrode of a capacitor so as to use PZT with a large dielectric constant for a capacitor dielectric film. Noble metal such as platinum is a source of contamination for silicon which not only deteriorates the characteristics of an element but also is difficult to process by conventional photo-etching in a predetermined shape.
Further, there are many problems in that a dielectric film consisting of the PZT or others cannot be protected against heat treatment of approximately 400xc2x0 C. or more and that long-term reliability is unclear and there is no prospect of practical use.
FIG. 91 shows a conventional memory cell provided with a crown-type capacitor on a data line and a metal oxide silicon field-effect transistor (MOSFET) in its adjacent peripheral circuits area. As shown in FIG. 91, a MOSFET in a memory cell area is constituted by a gate dielectric film 303, a gate electrode 304 and high-density N-type impurity areas 306 and 307, and the storage electrode 317 of a crown-type capacitor consisting of polycrystalline silicon is connected to this MOSFET via an opening formed on the high-density N-type impurity area 307 in clearance between a word line (the gate electrode 304) and a data line (a wiring electrode 310). Further, a capacitor dielectric film 318 is formed on this storage electrode 317 and a plate electrode 319 is provided on it.
The storage electrode 317 is cylindrical and the effective area of the capacitor is increased utilizing not only a flat portion but the inner face and the outer wall of a vertical portion. The effective area of the capacitor can be maximized by providing the storage electrode on the data line and further, the static capacitance of the capacitor can be readily increased by extending the height of the vertical region, that is, arranging the cylindrical storage electrode in a higher position.
A method of manufacturing a semiconductor memory device provided with such a crown-type or a cylinder-type capacitor will be briefly described below. First, a field oxide film 302 for insulating between elements is grown on a single crystalline silicon substrate 301 and the gate oxide film 303 of a MOSFET is formed. Next, a polycrystalline silicon film containing impurities in high density is formed as the gate electrode 304 and after patterning in a predetermined shape, high-density N-type impurity regions 306, 307 and 308 which are to function as the source and the drain regions of the MOSFET are formed on the single crystalline silicon substrate 301 by ion implantation in self-alignment. Next, after a silicon oxide film 309 is formed, an opening not shown is formed on the high-density N-type impurity region 306 of the MOSFET in a memory cell area, a polycrystalline silicon film including impurities in high density and a tungsten silicide film are formed in order as the data line 310 and are patterned in a predetermined shape. Next, after the silicon oxide film 311 is formed, an opening is formed on the high-density N-type impurity region 307 which is the source or the drain of the MOSFET in the memory cell area, a polycrystalline silicon film and a silicon oxide film are formed in order, after they are patterned in a predetermined shape, a polycrystalline silicon film is further formed, and the polycrystalline silicon film is left on the side wall of the silicon oxide film by removing the polycrystalline silicon film exposed in the flat portion by applying anisotropic dry etching to be the crown-type storage electrode 317. Next, after the capacitor dielectric film 318 is formed, a polycrystalline silicon film which is to function as the plate electrode 319 is further formed and is patterned so that it is in a predetermined shape. At last, a silicon oxide film 316 which is an interlayer dielectric film and aluminum wiring which is metal wiring 315 are formed, and the MOSFET and the memory cell of peripheral circuits are manufactured.
As described above, to further enhance the degree of integration of a DRAM, it is difficult to enhance the degree of integration of a DRAM consisting of the conventional stereoscopic cell and a semiconductor memory device which can solve the problem is strongly desired.
The conventional DRAM is described in, for example Japanese published unexamined utility model application No. Sho55-178894 and Japanese published unexamined patent applications No. Sho56-58253, No. Sho56-58254, No. Sho56-58255, No. Sho57-112066, No. Sho59-231351, No. Sho62-128168, No. Sho63-293967, No. Sho59-231851, No. H1-137666, No. H1-179449, No. H3-214670, No. H5-291526, No. Sho59-82761 and No. Sho62-213273.
In this specification, as shown in, for example FIG. 91, a capacitor wherein the section of a storage electrode is concave upward, and a capacitor dielectric film and a plate electrode are formed on the inner and outer faces of such a storage electrode is called a crown-type capacitor and a capacitor wherein a storage electrode, a capacitor dielectric film and a plate electrode are formed on the inner face of a trench is called a trench capacitor.
The object of the present invention is to solve the problems of the conventional stereoscopic memory cell and to provide a further minuter semiconductor memory device and its manufacturing method.
Another object of the present invention is to provide a semiconductor memory device provided with a capacitor which can secure sufficiently large storage capacity and its manufacturing method.
Further another object of the present invention is to provide a semiconductor memory device which can obtain sufficiently large storage capacity with forming a trench on a substrate and its manufacturing method.
The other object of the present invention is to provide a semiconductor memory device provided with large storage capacity wherein no large step height exists between a memory cell and its peripheral circuits and its manufacturing method.
To achieve the objects, according to the present invention, a trench which passes through a plurality of dielectric films laminated on a substrate is formed and a capacitor is formed using this trench.
Further another plural dielectric films are provided under the plural dielectric films and plural wiring layers are formed on these another plural dielectric films. Further another dielectric film is formed on the capacitor and another wiring layer is formed on it. Wiring which is not required to be pulled out on the dielectric film of the uppermost layer is formed in the plural wiring layers formed under the capacitor and only required minimum wiring is pulled out from each wiring layer under the capacitor onto the dielectric film of the uppermost layer via a conductive plug for interconnection which passes through the plural dielectric films. Therefore, as wiring can be formed without minute processing and the density of wiring may be low, the formation of wiring is extremely easy.
Referring to FIG. 1, the present invention will be described further in detail below. As shown in FIG. 1, a metal oxide semiconductor field-effect transistor (MOSFET) which functions as the switching transistor of a memory cell is connected with a word line 4 (the gate electrode of the MOSFET) and a bit line 7 for supplying and taking out charge are formed on a semiconductor substrate 1, further plural dielectric films 6, 8, 10, 12, 14, 16 and 18 are laminated and the surfaces are flattened.
A trench is formed through the dielectric films 14, 16 and 18 and a capacitor constituted by a lower electrode 19, a capacitor dielectric film 20 and a plate electrode 21 is formed inside this trench.
If a thick dielectric film is formed on the word line 4 and the bit line 7, an electrical connection to the word line 4 and the bit line 7 is required to be made via a plug for interconnection which passes through this thick dielectric film. However, it is difficult to form a contact hole and to embed metal. Therefore, according to the present invention, plural layers of wiring 9 and 11 are provided among the lower electrode 19 of the trench capacitor, the word line 4 and the bit line 7, and are used for a global word line for selecting a word line and a selector line for selecting a bit line. Therefore, wiring which is not required to be connected to the uppermost layer may be left buried as described above and a plug for interconnection which passes through the thick dielectric film is not required.
As the capacitor is provided over the plural layers of wiring 9 and 11 and heat treatment at approximately 800xc2x0 C. is performed, it is desirable that for the material of the wiring 9 and 11, tungsten and silicide which are proof against such heat treatment are used. Copper is desirable in that it has small resistance, however, the temperature of heat treatment against which it can be proof is 500xc2x0 C. or less. If a dielectric film with a high dielectric constant such as BST and PZT is used for a capacitor dielectric film, copper can be used for wiring material because the temperature at which a capacitor itself is formed is 400xc2x0 C. or less.
Referring to FIG. 1, the several wirings 9, 11 buried in an oxide are also used for a part of the wiring of a transistor in the peripheral circuits in addition to the word line 4 and the bit line 7 in the memory cell. Diffused regions 5 and 5xe2x80x2 and wiring 9xe2x80x2 are connected via wiring 7xe2x80x2 in the same layer as the bit-line 7. However, the wiring 9xe2x80x2 may.be directly connected to the diffused regions 5 and 5xe2x80x2. In that case, a part of the wiring 9xe2x80x2 is required to be barrier metal so as to prevent reaction between the diffused regions 5 and 5xe2x80x2 and the wiring 9xe2x80x2 respectively.
The capacitor is substantially formed only in the trench. The reason is to simplify a process of forming a capacitor. The lower electrode 19 of the capacitor consists of a polycrystalline silicon film including impurities in high density and is connected to the diffused region 5 of the MOSFET via polycrystalline film 13 for interconnection.
For the capacitor dielectric film 20, well-known various dielectric films such as a laminated film consisting of a silicon oxide film and a silicon nitride film, a laminated film consisting of a silicon oxide film and a tantalum pentoxide film, a stacked film consisting of a silicon nitride film and a tantalum pentoxide film, a stacked film consisting of a silicon oxide film, a silicon nitride film and a tantalum pentoxide film and a ferroelectric film such as BST and PZT may be used. However, when BST and PZT are used, noble metal such as platinum is required to be used for the lower electrode 19 and the plate electrode 21. Irregularities may be formed on the surface of the lower electrode 19 to increase its surface area.
It is desirable that the depth of the trench is approximately 2 xcexcm. However, when the trench is deep, the distance between the buried wiring 9 and 11 and wiring 23 in the uppermost layer respectively is long. As a result, it is difficult to form a plug for interconnection because a connecting hole with extremely large aspect ratio is required to be formed and such a connecting hole is required to be filled with metal.
However, according to the present invention, as shown in FIG. 1, the trench is formed not through a thick dielectric film, but through stacked plural dielectric films 14, 16 and 18. Therefore, when each dielectric film 14, 16 and 18 is formed, each connecting hole can be formed and can be filled with metal for connection. Hereby, metal 13 for connecting the lower electrode 19 and the diffused region 5 can be readily formed without forming the connecting hole with extremely large aspect ratio and filling it with metal especially. In addition, as described above, as the number of wiring which is required to be connected to the uppermost wiring layer is not many, high patterning accuracy is not required for the plug for interconnection used for pulling out wiring to the uppermost layer. This is one of the advantages of the present invention obtained by forming buried wiring.
Referring to FIG. 1, a reference number 1 denotes a semiconductor substrate, 2 denotes an element separating oxide film, 3 denotes the gate oxide film of a MOSFET, 4 denotes the gate electrode of the MOSFET which functions as a word line in a memory cell, 5 and 5xe2x80x2 denote the diffused regions of the MOSFET, 6 denotes an interlayer dielectric film, 7 denotes a bit line, 7xe2x80x2 denotes an interlayer for connecting the diffused region of a peripheral MosFET and its wiring, 8, 10, 12, 16, 18 and 22 denote an interlayer dielectric film, 9 and 11 denote buried wiring, 14 denotes an dielectric film, 15, 17 and 23 denote a plug for interconnection and 24 denotes wiring in the uppermost layer.
The step height can be prevented from being made effectively by the following method. That is, as schematically shown in FIG. 23, a stereoscopic capacitor 33 formed in a memory cell area and a wiring layer 34 in a peripheral circuit area are respectively provided on an dielectric film 32 formed on a silicon substrate 31 on which a MOSFET is formed or so that the upper face of the dielectric film 32 is in contact with the side portion of the capacitor 33. These wiring layer 34 and capacitor 33 are covered by an dielectric film 35,and wiring 36 in a memory cell array and wiring 37 in peripheral circuit are provided on the dielectric film 35.
As the wiring layer 34 of the peripheral circuit is formed on the dielectric film 32 in which a lower portion of the high stereoscopic capacitor 33 is formed, step height made by a capacitor 33 in a memory cell is reduced by the wiring layer 34. Therefore, even if the flat surface of the dielectric film 35 is formed and covers the capacitor 33 and the wiring layer 34, a through hole and a contact hole are not deepened in the peripheral circuit and the minute wiring 36 and 37 can be readily formed on the dielectric film 35 without disconnecting the wiring in the-through hole and the contact hole.
Further, according to the present invention, a wiring layer consisting of a first conductive film in the peripheral circuit area is provided on a first dielectric film and a second dielectric film can be further provided on it. A crown-type capacitor is formed in a concave portion formed by removing the predetermined portion of the first and second dielectric films. In this case, as shown in, for example FIG. 76, the upper face of aplate electrode 219 can be flattened and voltage can be applied to the plate electrode 219 from the top.